1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same. More specifically, the present invention relates to a semiconductor device including a transistor that has source and drain diffusion layers, and polysilicon contact plugs that connect the source and drain diffusion layers to interconnections. Further specifically, the present invention relates to a semiconductor device which includes reduced defects that reside in one or more diffusion layers and reduced junction leakage of current.
Priority is claimed on Japanese Patent Application No. 2006-259610, filed Sep. 25, 2006, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
Japanese Unexamined Patent Application, First Publication, No. 2003-17586 discloses a conventional structure of a memory cell transistor in a semiconductor memory device. FIG. 20 is a fragmentary cross sectional elevation view illustrating a conventional structure of a memory cell transistor in a semiconductor memory device, such as a DRAM. An insulating film 102 is formed in a semiconductor substrate that is not illustrated. The insulating film 102 defines active regions in the semiconductor substrate. A pair of transistors is formed in each active region. The paired transistors are commonly coupled to a bit line 101. In the active region, a p-well layer 103 and an n-channel doped layer 104 are provided. The n-channel doped layer 104 is provided over the p-well layer 103. The p-well layer 103 is given a substrate potential. The n-channel doped layer 104 determines a threshold voltage of the transistor. An n-type buried well is formed under the p-well layer 103.
Contact plugs 105 are provided, one of which is connected to the bit line 101. The contact plug 105 is made of polycrystal silicon. Gate electrodes 106 are provided in both sides of the contact plug 105. Agate insulating film 107 is provided over the n-channel doped layer 104 and under the contact plugs 105. Side spacers 108 are provided over the gate insulating film 107. Each side spacer 108 is interposed between the gate electrode 106 and the contact plug 105. N-diffusion layers 109 of a lower impurity concentration are provided in the n-channel doped layer 104. The n-diffusion layers 109 of the lower impurity concentration are separated by a channel region, over which the gate electrode 106 is positioned. The n-diffusion layer 109 of the lower impurity concentration is connected to the contact plug 105 which is further connected to the bit line 101. The other n-diffusion layers 109 of the lower impurity concentration are connected to the contact plugs 105 which are further connected to plugs 111 which are furthermore connected to capacitors 110.
The contact plug 105 of polycrystal silicon can be formed as follows. Contact holes are formed in an interlayer insulator 112. A chemical vapor deposition process is carried out to deposit a polycrystal silicon film that has a phosphorous concentration of about 2E20 cm−3. The polycrystal silicon film fills up the contact holes. In some cases, an additional phosphorous implantation process may be carried out following to the formation of the contact holes, thereby forming phosphorus-implanted regions 100. The phosphorus-implanted regions 100 are deeper than the n-diffusion layers 109 of the lower impurity concentration, for the purpose of field relaxation. The phosphorous implantation process can be carried out in accordance with the known conventional technique. Japanese Patent No. 3212150 discloses one conventional technique for phosphorous implantation process for the field relaxation.
An interlayer insulator 113 is provided over the interlayer insulator 112 and the contact plugs 105. An interlayer insulator 114 is provided over the interlayer insulator 113 and the bit line 101 and under the capacitors 110.
The conventional cell transistor structure of FIG. 20 can be formed as follows. A set of sequential processes from the contact-hole-making process to the contact plug formation process may generally be made. FIG. 21 is a fragmentary cross sectional elevation view illustrating a conventional cell transistor structure that is included in the conventional semiconductor device of FIG. 20.
Sequential processes having been carried out before the process for forming source and drain diffusion layers is carried out will not be described. Other sequential processes to be carried out after the process for forming the bit line 101 is carried out will also not be described.
As shown in FIG. 21, after the cell transistors have been formed, a silicon oxide film is deposited by a chemical vapor deposition process. The surface of the silicon oxide film is polished and planarized by a chemical mechanical polishing process. A resist film is applied on the planarized surface of the silicon oxide film. The resist film is patterned by a lithography process, thereby forming a resist pattern. The silicon oxide film is selectively etched by a dry etching process using the resist pattern as a mask, thereby forming contact holes 116. As a result, the n-diffusion layers 109 are partially shown under the contact holes 116. In other words, the contact holes 116 are formed so that the contact holes 116 are positioned over the n-diffusion layers 109. A phosphorus implantation process is carried out at an implantation-energy of 60 keV and a dose of about 1.5E13 cm−2 for the purpose of field relaxation.
A chemical vapor deposition process is carried out to deposit a phosphorous-doped polycrystal silicon film over the silicon oxide film and within the contact holes 116. The phosphorous-doped polycrystal silicon film is etched by an etching back process or polished by a chemical mechanical polishing process so as to leave the phosphorous-doped polycrystal silicon film only within the contact holes 116, while removing the phosphorous-doped polycrystal silicon film over the silicon oxide film. As a result, the contact plugs of phosphorous-doped polycrystal silicon film are formed in the contact holes 116.
A heat treatment is carried out at a temperature in the range of 950° C.-1050° C. for about 60 seconds in order to activate phosphorous in the contact plugs of phosphorous-doped polycrystal silicon film. One of the contact plugs is connected to the bit line. The other contact plugs are connected to the bottom electrodes of the capacitors.
The semiconductor device of FIG. 20 has the following disadvantages. H. Shirai et al., in Applied Physics Letters, Vol. 54, pp 1748-1750 (1989), reported as follows. A polycrystal silicon film is deposited on a single crystal silicon substrate. Then, a heat treatment is carried out at a temperature of at lowest 900° C. to cause crystal grain growth, thereby changing the crystalline structure of polycrystal silicon. Changing the crystalline structure of polycrystal silicon further causes absorption of silicon-interstitial in the single crystal silicon substrate under the polycrystal silicon film.
The crystal grains in polycrystal silicon have disordered crystal orientations Crystal grain boundary has irregular atomic arrangement. In contrast, regular atomic arrangement can be present inside each crystal grain. Crystal grain boundary is, in general, lower in the density of silicon atom than the inside of each crystal grain. Carrying out the heat treatment at a high temperature causes the growth of crystal grains in the polycrystal silicon film. Increasing the size of crystal grains upon the heat treatment decreases the volume density of crystal grain boundary. Silicon atoms are supplied to the crystal grain boundary, while the crystal grain is grown.
The present inventors investigated and confirmed the facts as follows. Application of a heat treatment to a polycrystal silicon film that contacts with a single crystal silicon substrate causes that silicon-interstitial in the single crystal silicon substrate is absorbed into the polycrystal silicon film. The present inventors found out that, in the process for forming cell transistors, many vacancy-type defects are generated in the vicinity of a p-n junction, while the heat treatment is carried out at a temperature in the range of 950° C.-1050° C. for about 60 seconds in order to activate phosphorous in the contact plugs of phosphorous-doped polycrystal silicon film.
FIG. 22 is a diagram illustrating a crystal structure model with vacancy-type defects. Vacancy=type defects are generated by changing the crystal structure of polycrystal silicon during a heat treatment. Silicon-interstitial in the source and drain diffusion layers are absorbed into the polycrystal silicon film that contacts with the source and drain diffusion layers, thereby generating vacancy-type defects in the source and drain diffusion layers. Namely, the vacancy-type defect concentration of the source and drain diffusion layers is increased by the heat treatment.
The present inventors also found out that the data retention time of the DRAM is likely to depend upon the concentration of vacancy-type defects in the vicinity of the p-n junction of the cell transistor. FIG. 23 is a diagram illustrating dependency of data retention time of DRAM upon the concentration of vacancy-type defects. As the concentration of vacancy-type defects is increased, the data retention time is decreased.
The presence of vacancy-type defects in a depletion layer can increase the leakage of p-n junction current. Increasing the leakage of p-n junction current shortens the data retention time of the DRAM. In other words, increasing the leakage of p-n junction current deteriorates data holding characteristics of the DRAM. The vacancy-type defect is formed by eliminating a silicon atom from a lattice of the crystal structure. Other silicon atoms adjacent to the empty lattice, from which silicon atom was eliminated, have tensile strains. Thus, the vacancy-type defects are likely to be stabled at a compressive strain field.
FIG. 24 is a diagram illustrating the dependency of data retention time upon compressive strain of a depletion layer of the DRAM cell transistor. Increasing the compressive strain of the depletion layer shortens the data retention time. This demonstrates that increasing the compressive strain of the depletion layer increases the concentration of vacancy-type defects as generated. The cell transistors of the DRAM have polysilicon plugs. Thus, increasing the concentration of vacancy-type defects increases the leakage of junction current and deteriorates the information holding characteristics.
It is necessary to suppress the absorption of silicon-interstitial into the polycrystal silicon in the contact plug while a heat treatment is carried out at high temperature after the contact plug of polycrystal silicon film has been formed in the contact hole.
FIG. 25A is a photograph showing a cross section of a silicon substrate having an interface with a polysilicon film that extends over the silicon substrate. FIG. 25B is a photograph showing a cross section of a silicon substrate having an exposed surface, free of any polysilicon film. A single crystal silicon wafer free of any polysilicon film was prepared as a first sample. Another single crystal silicon wafer with an overlying polysilicon film was prepared as a second sample. After both the first and second samples were then subjected to a heat treatment at 1000° C. for 10 hours, the distribution of oxygen precipitate in the silicon substrate was observed by a known observation method using a defect etchant. The first and second samples of wafer were subjected to a heat treatment and the wafers were cleaved. The cleaved facets of the wafers were then exposed to a detect etchant such as a fluoro-nitric acid solution, thereby wet-etching the cleaved facets of the wafers. The cleaved facets of the wafers were then observed by an optical microscope.
As shown in FIG. 25A, oxygen precipitate was observed in the silicon substrate of the first ample in the vicinity of the interface between the silicon substrate and the polycrystal silicon film. As shown in FIG. 25B, almost no oxygen precipitate was observed in the silicon substrate of the second sample.
FIG. 25C is a diagram illustrating the mechanism of generating vacancy-type defects in a single crystal structure of silicon by heat treatment. A single crystal silicon substrate 100 has a shallow trench isolation film 110 and an n-type diffusion layer 120. Agate insulating film is provided on the surface of the silicon substrate 100. Agate electrode 130 is formed on the gate insulating film. A polysilicon contact plug 140 is provided which contacts with the silicon crystal silicon diffusion region 120. An inter-layer insulator 150 is provided which covers the shallow trench isolation film 110, the polysilicon contact plug 140, the gate electrode 130, and the gate insulating film. Grain boundary in the polycrystal silicon contact plug 140 has silicon deficiency which causes that silicon atoms are moved from the n-type diffusion layer 120 to the polycrystal silicon contact plug 140, thereby forming vacancy-type defects in the n-type diffusion layer 120.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device and/or method of forming a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.